US 11,756,648 B1
Semiconductor device having redundancy word lines
Minari Arai, Saitama (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Mar. 10, 2022, as Appl. No. 17/692,049.
Int. Cl. G11C 29/00 (2006.01); G11C 29/18 (2006.01); G11C 29/36 (2006.01); G11C 11/406 (2006.01); G11C 29/44 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/785 (2013.01) [G11C 11/40615 (2013.01); G11C 11/40622 (2013.01); G11C 29/18 (2013.01); G11C 29/36 (2013.01); G11C 29/44 (2013.01); G11C 2029/1202 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of first register circuits each configured to store a corresponding one of a plurality of bits of a first address, the plurality of bits of the first address being grouped into a first bit group and a second bit group; and
a comparing circuit configured to compare the first address stored in the plurality of first register circuits with a second address, a plurality of bits of the second address being grouped into a third bit group and a fourth bit group,
wherein the comparing circuit includes a first circuit section configured to compare each bit of the first bit group with an associated bit of the third bit group and a second circuit section configured to compare each bit of the second bit group with an associated bit of the fourth bit group,
wherein, in a first operation mode, the comparing circuit is configured to activate a match signal when the first circuit section detects that the first bit group matches with the third bit group and the second circuit section detects that the second bit group matches with the fourth bit group, and
wherein, in a second operation mode, the comparing circuit is configured to activate the match signal when the first circuit section detects that the first bit group matches with the third bit group regardless of the second and fourth bit groups.