US 11,756,635 B2
Decision for executing full-memory refresh during memory sub-system power-on stage
Tingjun Xie, Milpitas, CA (US); Zhenlei Shen, Milpitas, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 28, 2022, as Appl. No. 17/851,830.
Application 17/851,830 is a continuation of application No. 16/510,735, filed on Jul. 12, 2019, granted, now 11,404,131.
Prior Publication US 2022/0328111 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 16/26 (2006.01); G06F 3/06 (2006.01)
CPC G11C 16/3418 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0658 (2013.01); G06F 3/0683 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of memory devices storing a set of codewords; and
a processing device, operatively coupled to the plurality of memory devices, to perform operations comprising:
detecting a power-on of the system;
determining a read-retry trigger rate (TR) based on reading a subset of the codewords during a time interval directly after actual initialization of the plurality of memory devices, wherein the time interval comprises a time period before entering a normal operating mode, and no full-memory refresh operation is performed during the normal operating mode;
determining whether the TR satisfies a threshold criterion; and
in response to the TR not satisfying the threshold criterion, initializing the full-memory refresh operation of the plurality of memory devices.