US 11,756,631 B2
Adjusting read voltage levels based on a programmed bit count in a memory sub-system
Douglas E. Majerus, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 13, 2022, as Appl. No. 17/838,594.
Application 17/838,594 is a continuation of application No. 16/822,561, filed on Mar. 18, 2020, granted, now 11,361,830.
Prior Publication US 2022/0310176 A1, Sep. 29, 2022
Int. Cl. G11C 16/26 (2006.01); G11C 16/12 (2006.01); G11C 16/34 (2006.01); G11C 16/30 (2006.01); G11C 16/14 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/12 (2013.01); G11C 16/14 (2013.01); G11C 16/30 (2013.01); G11C 16/349 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
establishing, by a processing device, a target value of programmed bits of a first programming distribution of a set of programming distributions associated with a memory device;
applying a first read voltage level to a word line portion of the memory device;
determining a count of programmed bits in the set of programming distributions corresponding to the first read voltage level;
determining a measured ratio of the programmed bits of the first programming distribution to the count of programmed bits in the set of programming distributions;
comparing the target value to the measured ratio to determine a comparison result; and
executing an action in view of the comparison result.