US 11,756,623 B2
Semiconductor storage device
Hiroshi Maejima, Setagaya Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Dec. 29, 2021, as Appl. No. 17/565,241.
Application 16/842,633 is a division of application No. 16/391,041, filed on Apr. 22, 2019, granted, now 10,643,702, issued on May 5, 2020.
Application 17/565,241 is a continuation of application No. 17/152,355, filed on Jan. 19, 2021, granted, now 11,244,726.
Application 17/152,355 is a continuation of application No. 16/842,633, filed on Apr. 7, 2020, granted, now 10,902,918, issued on Jan. 26, 2021.
Application 16/391,041 is a continuation of application No. 16/022,568, filed on Jun. 28, 2018, granted, now 10,276,241, issued on Apr. 30, 2019.
Application 16/022,568 is a continuation of application No. 15/583,609, filed on May 1, 2017, granted, now 10,014,054, issued on Jul. 3, 2018.
Application 15/583,609 is a continuation of application No. 14/788,629, filed on Jun. 30, 2015, granted, now 9,672,927, issued on Jun. 6, 2017.
Application 14/788,629 is a continuation of application No. 13/784,735, filed on Mar. 4, 2013, granted, now 9,111,592, issued on Aug. 18, 2015.
Claims priority of application No. 2012-144628 (JP), filed on Jun. 27, 2012.
Prior Publication US 2022/0122666 A1, Apr. 21, 2022
Int. Cl. G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 5/06 (2006.01); G11C 7/06 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC G11C 16/0483 (2013.01) [G11C 5/063 (2013.01); G11C 7/06 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A semiconductor storage device, comprising:
a plurality of word lines extending in a first direction and a second direction, and separated from each other in a third direction, the first, second, and third directions crossing one another;
a plurality of sense amplifier circuits partially overlapping the word lines when viewed in the third direction;
a plurality of memory strings intersecting the word lines, and extending in the third direction;
a plurality of first bit lines extending in the first direction and separated from each other in the second direction;
a plurality of second bit lines between the word lines and the sense amplifier circuits in the third direction, and extending in the first direction; and
a plurality of contact plugs extending in the third direction, respectively connected connecting the first bit lines and the second bit lines, and arranged such that one of the a first contact plug of the plurality of contact plugs, which is between second and third contact plugs of the plurality of contact plugs in the second direction, is offset with respect to the second and third contact plugs in the first direction.