US 11,756,621 B2
Architecture for fast content addressable memory search
Tomoko Ogura Iwasaki, San Jose, CA (US); and Manik Advani, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 9, 2022, as Appl. No. 17/690,698.
Application 17/690,698 is a continuation of application No. 17/318,826, filed on May 12, 2021, granted, now 11,295,814.
Application 17/318,826 is a continuation of application No. 16/727,671, filed on Dec. 26, 2019, granted, now 11,031,080.
Prior Publication US 2022/0199161 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 15/00 (2006.01); G11C 15/04 (2006.01)
CPC G11C 15/046 (2013.01) [G11C 15/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a content addressable memory (CAM) block; and
a processing device coupled to the CAM block, the processing device to perform operations comprising:
providing, as input to search lines of the CAM block, a search pattern, the search pattern being based on an input search word, the providing of the search pattern comprising:
providing a first voltage signal representing the search word; and
providing a second voltage signal representing an inverse of the search word;
the search pattern causing a string in the CAM block to provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string, the page buffer storing data based on the signal; and
outputting a location of the data entry within the CAM block determined based on a count of a number of shifts performed to serially shift out on the data from the page buffer.