US 11,756,614 B2
Phase change memory device, system including the memory device, and method for operating the memory device
Maurizio Francesco Perroni, Messina (IT); Fabio Enrico Carlo Disegni, Spino d'adda (IT); Davide Manfré, Pandino (IT); and Cesare Torti, Pavia (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Apr. 4, 2022, as Appl. No. 17/657,861.
Application 17/657,861 is a continuation of application No. 17/119,979, filed on Dec. 11, 2020, granted, now 11,328,768.
Claims priority of application No. 102019000024253 (IT), filed on Dec. 17, 2019.
Prior Publication US 2022/0230682 A1, Jul. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 7/02 (2006.01); G11C 7/06 (2006.01)
CPC G11C 13/0004 (2013.01) [G11C 7/02 (2013.01); G11C 7/06 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A phase-change memory device, comprising:
a memory array including a first sector having a first memory portion of direct memory cells, and a second sector having a second memory portion of direct memory cells;
a reading stage including a first sense amplifier configured to read a logic datum stored in a direct memory cell of the first sector, and a second sense amplifier configured to read a logic datum stored in a direct memory cell of the second sector;
a global column decoder functionally connected between the reading stage and the first and second sectors;
a first main bitline, having a first parasitic capacitance, which extends between the direct memory cells of the first sector and the global column decoder;
a second main bitline, having a second parasitic capacitance, which extends between the direct memory cells of the second sector and the global column decoder;
at least one reference-current generator coupled to the first and second sense amplifiers for supplying a reference reading current during a first operating mode of single-ended reading; and
a controller configured to execute, in order to read the logic datum stored in the first sector during the first operating mode, the operations of:
selecting a direct memory cell to be read belonging to the first memory portion of the first sector;
connecting, via the global column decoder, the first main bitline to a first input of the first sense amplifier, thus coupling the first parasitic capacitance to the first input of the first sense amplifier and enabling a flow of current between the direct memory cell to be read in the first sector and the first input of the first sense amplifier; and
connecting the reference-current generator to a second input of the first sense amplifier, thus enabling a flow of the reference reading current towards the second input of the first sense amplifier;
the controller being moreover configured to execute, in order to read the logic datum stored in the second sector during the first operating mode, the operations of:
selecting a direct memory cell to be read belonging to the second memory portion of the second sector;
connecting, via the global column decoder, the second main bitline to a first input of the second sense amplifier, thus coupling the second parasitic capacitance to the first input of the second sense amplifier and enabling a flow of current between the direct memory cell to be read in the second sector and the first input of the second sense amplifier; and
connecting the reference-current generator to a second input of the second sense amplifier, thus enabling a flow of the reference reading current towards the second input of the second sense amplifier.