US 11,756,612 B2
All levels dynamic start voltage programming of a memory device in a memory sub-system
Jun Xu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 26, 2021, as Appl. No. 17/301,139.
Prior Publication US 2022/0310158 A1, Sep. 29, 2022
Int. Cl. G11C 11/34 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01)
CPC G11C 11/5628 (2013.01) [G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of memory cells configured as multi-level cell (MLC) memory; and
control logic, operatively coupled with the memory array, to perform operations comprising:
identifying a set of the plurality of memory cells configured as MLC memory to be programmed during a program operation;
determining respective magnitudes for a plurality of programming pulses, the respective magnitudes corresponding to respective programming levels of a plurality of programming levels, wherein indications of the respective magnitudes are stored in a data structure managed by the control logic, and wherein the respective magnitudes for the plurality of programming pulses are based at least in part on a previous program operation;
causing the plurality of programming pulses to be applied, without intermediate program verify operations, to at least a portion of the set of the plurality of memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to the respective programming levels of the plurality of programming levels as part of the program operation, wherein the plurality of programming pulses each have respective magnitudes that decrease over time to cover a respective subset of the respective programming levels of the plurality of programming levels, and wherein each successive programming pulse has an initial magnitude that is lower than a final magnitude of a previous programming pulse; and
responsive to the plurality of programming pulses being applied, performing a program verify operation to verify whether the memory cells in the set of memory cells configured as MLC memory were programmed to the respective programming levels of the plurality of programming levels.