US 11,756,604 B2
Managing write disturb for units of memory in a memory sub-system using a randomized refresh period
Charles See Yeung Kwong, Redwood City, CA (US); and Seungjune Jeon, Santa Clara, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 16, 2022, as Appl. No. 17/946,612.
Application 17/946,612 is a continuation of application No. 17/402,984, filed on Aug. 16, 2021, granted, now 11,495,279.
Prior Publication US 2023/0051408 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/406 (2006.01); G11C 29/42 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/40622 (2013.01) [G11C 11/4096 (2013.01); G11C 11/40615 (2013.01); G11C 29/42 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
detecting a memory access operation performed on a first memory unit of the memory device;
modifying a value of a counter associated with the first memory unit wherein the value of the counter corresponds to a number of occurrences of memory access operations performed on the first memory unit;
determining that the value of the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a margin of an average number of memory access operations; and
responsive to determining that the value of the counter satisfies the threshold criterion, performing a refresh operation on a second memory unit.