CPC G11C 11/2273 (2013.01) [G11C 11/221 (2013.01)] | 20 Claims |
1. A method, comprising:
generating a first signal at a gate of a first transistor based at least in part on coupling a memory cell with a first access line;
generating a second signal at a gate of a second transistor based at least in part on coupling a reference voltage source with a second access line;
generating a third signal at a drain of the first transistor and a fourth signal at a drain of the second transistor based at least in part on generating the first signal, generating the second signal, and coupling a source of the first transistor with a source of the second transistor; and
determining, at a sense amplifier having a first node coupled with the drain of the first transistor and a second node coupled with the drain of the second transistor, a logic state stored by the memory cell based at least in part on comparing the third signal with the fourth signal.
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