US 11,756,601 B2
Differential sensing for a memory device
Ferdinando Bedeschi, Biassono (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 12, 2021, as Appl. No. 17/499,322.
Application 17/499,322 is a continuation of application No. 16/895,956, filed on Jun. 8, 2020, granted, now 11,152,049.
Prior Publication US 2022/0101905 A1, Mar. 31, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 11/221 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
generating a first signal at a gate of a first transistor based at least in part on coupling a memory cell with a first access line;
generating a second signal at a gate of a second transistor based at least in part on coupling a reference voltage source with a second access line;
generating a third signal at a drain of the first transistor and a fourth signal at a drain of the second transistor based at least in part on generating the first signal, generating the second signal, and coupling a source of the first transistor with a source of the second transistor; and
determining, at a sense amplifier having a first node coupled with the drain of the first transistor and a second node coupled with the drain of the second transistor, a logic state stored by the memory cell based at least in part on comparing the third signal with the fourth signal.