US 11,756,596 B1
Transition structures for three-dimensional memory arrays
Shuangqiang Luo, Boise, ID (US); Indra V. Chary, Boise, ID (US); and Lifang Xu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 24, 2022, as Appl. No. 17/752,332.
Int. Cl. G11C 7/18 (2006.01); G11C 7/10 (2006.01); H01L 25/065 (2023.01); H01L 23/48 (2006.01); H10B 99/00 (2023.01)
CPC G11C 7/18 (2013.01) [G11C 7/1027 (2013.01); H01L 23/481 (2013.01); H01L 25/0652 (2013.01); H10B 99/00 (2023.02)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of access line decoders at least partially in a substrate;
a plurality of word line plates arranged vertically above the substrate and separated from each other by respective dielectric layers, each word line plate comprising a plurality of word line members that each extend in a first horizontal direction and into a memory region;
a first plurality of vias extending vertically through the plurality of word line plates, the first plurality of vias arranged in rows extending in the first horizontal direction and columns extending in a second horizontal direction, each via of the first plurality of vias coupled with a respective access line decoder of the plurality of access line decoders; and
a second plurality of vias extending vertically through the plurality of word line plates, each via of the second plurality of vias electrically isolated from the plurality of access line decoders, and a subset of the second plurality of vias arranged in a column extending in the second horizontal direction and in between the first plurality of vias and the memory region in the first horizontal direction.