CPC G11C 7/12 (2013.01) [G11C 5/147 (2013.01); G11C 8/08 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a precharge circuit operably connected to a memory cell;
a first switch circuit operably connected between the precharge circuit and a first signal line providing a first voltage level that is greater than a low voltage level;
a second switch circuit operably connected between the precharge circuit and a second signal line providing a second voltage level that is greater than the low voltage level and less than the first voltage level;
a voltage level detector operably connected to the second signal line; and
a charge storage device operably connected to the second signal line.
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