CPC G11C 7/106 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); G11C 7/14 (2013.01); G11C 7/222 (2013.01)] | 16 Claims |
1. A memory device comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells;
a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
a voltage generation device to selectively apply voltages to the plurality of access lines; and
control logic configured to:
open the array of memory cells for multiple read operations;
read first page data from respective memory cells coupled to a selected access line of the plurality of access lines for a first block of memory cells of the array of memory cells;
read second page data from the respective memory cells coupled to the selected access line for a second block of memory cells of the array of memory cells; and
close the array of memory cells subsequent to reading the first page data and the second page data,
wherein the first page data comprises a first logical page and the second page data comprises a second logical page.
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