US 11,756,594 B2
Memory devices for multiple read operations
Eric N. Lee, San Jose, CA (US); Kishore Kumar Muchherla, Fremont, CA (US); Jeffrey S. McNeil, Nampa, ID (US); and Jung-Sheng Hoei, Newark, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 1, 2021, as Appl. No. 17/463,789.
Claims priority of provisional application 63/126,001, filed on Dec. 16, 2020.
Prior Publication US 2022/0189517 A1, Jun. 16, 2022
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 7/14 (2006.01)
CPC G11C 7/106 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); G11C 7/14 (2013.01); G11C 7/222 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory device comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells;
a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
a voltage generation device to selectively apply voltages to the plurality of access lines; and
control logic configured to:
open the array of memory cells for multiple read operations;
read first page data from respective memory cells coupled to a selected access line of the plurality of access lines for a first block of memory cells of the array of memory cells;
read second page data from the respective memory cells coupled to the selected access line for a second block of memory cells of the array of memory cells; and
close the array of memory cells subsequent to reading the first page data and the second page data,
wherein the first page data comprises a first logical page and the second page data comprises a second logical page.