CPC G06T 1/20 (2013.01) [G06F 13/4027 (2013.01)] | 22 Claims |
1. A multi-chip module comprising:
a plurality of semiconductor dies and a plurality of die-to-die interconnects, the plurality of semiconductor dies comprising:
a first semiconductor die including:
a plurality of graphics processing resources including a graphics multiprocessor, the graphics multiprocessor coupled with a first cache memory;
an interconnect fabric coupled with the first cache memory, wherein the first cache memory is associated with the graphics multiprocessor; and
a second cache memory coupled with the interconnect fabric, the interconnect fabric to couple the second cache memory with the first cache memory; and
a second semiconductor die coupled with the first semiconductor die in a 2.5-dimensional (2.5D) or 3-dimensional (3D) arrangement, the second semiconductor die including a third cache memory, wherein the third cache memory is accessible to the plurality of graphics processing resources of the first semiconductor die.
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