CPC G06F 30/333 (2020.01) [H03K 19/17732 (2013.01); H03K 19/17764 (2013.01); G06F 11/267 (2013.01); G06F 11/27 (2013.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); G06F 2115/08 (2020.01); H01L 22/34 (2013.01); H01L 25/00 (2013.01)] | 20 Claims |
16. A method, comprising:
providing scan data to each of a plurality of instances of an intellectual property core within an integrated circuit through scan data pipeline circuitry;
providing one or more scan control signals to each of the plurality of instances through scan control signal pipeline circuitry;
wherein the scan data pipeline circuitry and the scan control signal pipeline circuitry to each respective one of the plurality of instances are matched; and
for each instance of the plurality of instances, selectively suppressing a scan clock to the instance for a number of clock cycles using a wave shaping circuit associated with the instance, wherein for each instance the selectively suppressing is based on detecting a trigger event on the one or more scan control signals provided to the instance.
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