US 11,755,804 B2
Hybrid synchronous and asynchronous control for scan-based testing
Albert Shih-Huai Lin, Mountain View, CA (US); Rambabu Nerukonda, Sunnyvale, CA (US); Niravkumar Patel, San Jose, CA (US); and Amitava Majumdar, San Jose, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Dec. 28, 2021, as Appl. No. 17/646,184.
Prior Publication US 2023/0205959 A1, Jun. 29, 2023
Int. Cl. G06F 30/333 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); G06F 30/20 (2020.01); G06F 11/267 (2006.01); G06F 11/27 (2006.01); H01L 25/00 (2006.01); H03K 19/17732 (2020.01); H03K 19/17764 (2020.01); G06F 115/08 (2020.01); H01L 21/66 (2006.01)
CPC G06F 30/333 (2020.01) [H03K 19/17732 (2013.01); H03K 19/17764 (2013.01); G06F 11/267 (2013.01); G06F 11/27 (2013.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); G06F 2115/08 (2020.01); H01L 22/34 (2013.01); H01L 25/00 (2013.01)] 20 Claims
OG exemplary drawing
 
16. A method, comprising:
providing scan data to each of a plurality of instances of an intellectual property core within an integrated circuit through scan data pipeline circuitry;
providing one or more scan control signals to each of the plurality of instances through scan control signal pipeline circuitry;
wherein the scan data pipeline circuitry and the scan control signal pipeline circuitry to each respective one of the plurality of instances are matched; and
for each instance of the plurality of instances, selectively suppressing a scan clock to the instance for a number of clock cycles using a wave shaping circuit associated with the instance, wherein for each instance the selectively suppressing is based on detecting a trigger event on the one or more scan control signals provided to the instance.