US 11,755,798 B2
Logic circuits with reduced transistor counts
Chi-Lin Liu, Hsinchu (TW); Jerry Chang-Jui Kao, Hsinchu (TW); Wei-Hsiang Ma, Hsinchu (TW); Lee-Chung Lu, Hsinchu (TW); Fong-Yuan Chang, Hsinchu (TW); Sheng-Hsiung Chen, Hsinchu (TW); and Shang-Chih Hsieh, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 7, 2021, as Appl. No. 17/340,662.
Application 17/340,662 is a continuation of application No. 15/930,010, filed on May 12, 2020, granted, now 11,030,366.
Application 15/930,010 is a continuation of application No. 15/936,712, filed on Mar. 27, 2018, granted, now 10,664,565, issued on May 26, 2020.
Claims priority of provisional application 62/509,048, filed on May 19, 2017.
Prior Publication US 2021/0294958 A1, Sep. 23, 2021
Int. Cl. G06F 30/327 (2020.01); G06F 111/06 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 2111/06 (2020.01); G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A logic circuit comprising:
first and second inverters; and
transistors configured such that:
first and second sets thereof represent corresponding first and second NAND circuits;
a third set thereof represents a transmission gate; and
a fourth set thereof represents a transmission-gate-substitute (TGS) circuit; and
wherein:
a first input of each of the first and second NAND circuits is configured to receive corresponding first and second data signals;
a second input of each of the first and second NAND circuits is configured to receive an enable signal;
the first inverter is configured to receive an output of the first NAND circuit;
the third and fourth sets are arranged as a combination circuit, representing one of an exclusive OR (XOR) circuit or an exclusive NOR (XNR) circuit, and being configured to receive:
an output of the second NAND circuit as a data input; and
an output of the first inverter and an output of the second NAND circuit as control inputs;
the second inverter is configured to receive an output of the combination circuit; and
an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function applied to the first and second data signals and the enable signal.