US 11,755,785 B2
System and method of limiting access of processors to hardware resources
Martin Mienkina, Bystrice Nad Olsi (CZ); Carl Culshaw, Wigan (GB); Larry Alan Woodrum, Austin, TX (US); and David Eromosele, Munich (DE)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Aug. 3, 2020, as Appl. No. 16/983,694.
Prior Publication US 2022/0035953 A1, Feb. 3, 2022
Int. Cl. G06F 21/70 (2013.01); G06F 21/44 (2013.01)
CPC G06F 21/70 (2013.01) [G06F 21/44 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processing system, comprising:
a plurality of processors each assigned a corresponding one of a plurality of identifiers;
a plurality of peripheral slots each located within an addressable peripheral space;
a plurality of hardware resources each placed into a corresponding one of the plurality of peripheral slots, wherein the plurality of hardware resources comprises:
at least one direct memory access (DMA) device supporting at least one DMA channel; and
a plurality of general-purpose input/output (GPIO) pins;
gateway circuitry that is programmed to control access of the plurality of hardware resources only by a processor that provides a matching identifier; and
a virtualization wrapper defining a first virtual pin group comprising a subset of the plurality of GPIO pins and configured to place the first virtual pin group into a first peripheral slot, wherein the gateway circuitry is programmed with a first domain identifier of a first processor for controlling access to the first virtual pin group.