CPC G06F 13/4221 (2013.01) [G06F 9/30101 (2013.01); G06F 9/546 (2013.01); G06F 13/387 (2013.01); G06F 13/4027 (2013.01); G06F 2213/0026 (2013.01)] | 14 Claims |
1. A system comprising:
a physical interface for a PCI express (PCIe) PIPE5 controller including a plurality of media access control (MAC) registers;
a PIPE4 device; and
a converter including a first interface coupled to the PIPE5 controller through a message bus interface, a second interface coupled to the PIPE4 device through a PCIe link and a plurality of physical (PHY) registers, wherein, when a first message bus interface signal is received from the PIPE5 controller, the first interface finds a target PHY register among the plurality of PHY registers based on the first message bus interface signal, and the second interface generates a first link interface signal associated with the target PHY register and outputs the first link interface signal to the PIPE4 device, and
wherein, when a second link interface signal is received from the PIPE4 device, the first interface finds a target MAC register among the plurality of MAC registers based on the second link interface signal and outputs a second message bus interface signal to write to the target MAC register based on the second link interface signal.
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