US 11,755,524 B2
Controller area network apparatus
Matthias Berthold Muth, Stelle (DE)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on May 11, 2021, as Appl. No. 17/302,752.
Claims priority of application No. 20180102 (EP), filed on Jun. 15, 2020; and application No. 20196322 (EP), filed on Sep. 15, 2020.
Prior Publication US 2021/0389972 A1, Dec. 16, 2021
Int. Cl. H03M 5/06 (2006.01); G06F 13/40 (2006.01); H03M 5/14 (2006.01); H04L 12/40 (2006.01); H03M 5/20 (2006.01); H03M 13/33 (2006.01)
CPC G06F 13/4072 (2013.01) [H03M 5/145 (2013.01); H03M 5/20 (2013.01); H03M 13/33 (2013.01); H04L 2012/40215 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A Controller Area Network (CAN) bit stream apparatus for a CAN controller, the apparatus configured to:
receive an incoming bit stream from a CAN transceiver;
detect rising edges in the incoming bit stream;
detect, separately, falling edges in the incoming bit stream; and
generate a restored non-return-to-zero coded bit stream based at least on said detected falling edges and said detected rising edges;
wherein generating the restored non-return-to zero coded bit stream based at least on said detected falling edges and said detected rising edges comprises:
generating a first logic state bit in said restored non-return-to-zero coded bit stream in response to detecting a first rising edge in the incoming bit stream;
generating a second logic state bit in said restored non-return-to-zero coded bit stream in response to detecting a first falling edge in the incoming bit stream;
generating a further first logic state bit in said restored non-return-to-zero coded bit stream subsequent to said first logic state bit following the detection of the first rising edge and prior to detection of a directly subsequent edge based on the elapse of a predetermined bit time; and
generating a further second logic state bit in said restored non-return-to-zero coded bit stream subsequent to said second logic state bit following the detection of the first falling edge and prior to detection of a directly subsequent edge based on the elapse of the predetermined bit time.