US 11,755,521 B2
Folded memory modules
Amir Amirkhany, Sunnyvale, CA (US); Suresh Rajan, San Jose, CA (US); Ravindranath Kollipara, Palo Alto, CA (US); Ian Shaeffer, Los Gatos, CA (US); and David A. Secker, San Jose, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jun. 29, 2022, as Appl. No. 17/809,688.
Application 17/809,688 is a continuation of application No. 16/950,861, filed on Nov. 17, 2020, granted, now 11,409,682.
Application 16/950,861 is a continuation of application No. 16/525,315, filed on Jul. 29, 2019, granted, now 10,866,916, issued on Dec. 15, 2020.
Application 16/525,315 is a continuation of application No. 15/289,785, filed on Oct. 10, 2016, granted, now 10,380,053, issued on Aug. 13, 2019.
Application 15/289,785 is a continuation of application No. 14/182,986, filed on Feb. 18, 2014, granted, now 9,489,323, issued on Nov. 8, 2016.
Claims priority of provisional application 61/767,097, filed on Feb. 20, 2013.
Prior Publication US 2022/0398206 A1, Dec. 15, 2022
Int. Cl. G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 12/00 (2006.01); G06F 13/00 (2006.01)
CPC G06F 13/4022 (2013.01) [G06F 12/00 (2013.01); G06F 13/00 (2013.01); G06F 13/1673 (2013.01); G06F 13/1694 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory controller for controlling a set of memory modules, the memory controller comprising:
a command/address interface to communicate commands and addresses to at least a first memory module and a second memory module;
a data interface including at least a first subset of memory controller data pins to communicate data with the first memory module and at least a second subset of memory controller data pins to communicate data with the second memory module;
a select interface to select between a first rank of memory devices and a second rank of memory devices,
wherein the first rank of memory devices includes at least one memory device of the first memory module coupled to the first subset of the memory controller data pins and at least one memory device of the second memory module coupled to the second subset of the memory controller data pins; and
wherein the second rank of memory devices including at least one memory device of the first memory module coupled to the first subset of the memory controller data pins and at least one memory device of the second memory module coupled to second subset of the memory controller data pins; and
configuration control logic to control a connectivity configuration of at least the first memory module by controlling which memory module data pins of the first memory module are enabled for communicating with the memory controller.