US 11,755,515 B2
Translation system for finer grain memory architectures
Brent Keeth, Boise, ID (US); Richard C. Murphy, Boise, ID (US); and Elliott C. Cooper-Balis, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 2, 2022, as Appl. No. 17/685,212.
Application 17/685,212 is a continuation of application No. 16/058,868, filed on Aug. 8, 2018, granted, now 11,281,608.
Claims priority of provisional application 62/597,304, filed on Dec. 11, 2017.
Prior Publication US 2022/0188253 A1, Jun. 16, 2022
Int. Cl. G06F 13/28 (2006.01); G06F 12/10 (2016.01); G06F 13/16 (2006.01); G06F 3/06 (2006.01); G06F 12/1027 (2016.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G06F 13/28 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0661 (2013.01); G06F 12/10 (2013.01); G06F 12/1027 (2013.01); G06F 13/1668 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); G06F 2212/65 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a host device configured to communicate with memory devices using a first communication protocol;
a memory device comprising logic for implementing at least a portion of operations associated with a memory controller of the memory device and being configured to communicate with the host device using a second communication protocol different than the first communication protocol;
a silicon interposer comprising a first area for the host device, a second area for memory devices configured to communicate with the host device using the first communication protocol, and a first plurality of channels between the first area and the second area, wherein the host device is positioned on the first area of the silicon interposer and the first plurality of channels support the first communication protocol; and
a translation device positioned on the second area of the silicon interposer, distinct from the logic for implementing at least the portion of operations associated with the memory controller, and configured to communicate with the host device via the first plurality of channels in the silicon interposer using the first communication protocol and with the memory device via a second plurality of channels in an organic substrate that is coupled with the translation device and the memory device using the second communication protocol.