US 11,755,511 B2
Data bus inversion using multiple transforms
Krishnan Srinivasan, San Jose, CA (US); and Sagheer Ahmad, Cupertino, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Aug. 25, 2021, as Appl. No. 17/411,891.
Prior Publication US 2023/0069505 A1, Mar. 2, 2023
Int. Cl. G06F 13/20 (2006.01); G06F 9/445 (2018.01)
CPC G06F 13/20 (2013.01) [G06F 9/44505 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transmitter circuitry comprising:
inversion circuitry configured to generate a first transformed data word by inverting one or more of a plurality of bits of a first data word;
first transform circuitry configured to generate a second transformed data word by performing a first invertible operation on the first data word and a second data word; and
selection circuitry configured to:
select one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word; and
output the selected data word.