US 11,755,496 B1
Memory de-duplication using physical memory aliases
Peter Barry, Limerick (IE); Adi Habusha, Alonei Abba (IL); and Martin Pohlack, Dresden (DE)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/547,888.
Int. Cl. G06F 12/1009 (2016.01); G06F 12/0882 (2016.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 12/0238 (2013.01); G06F 12/0646 (2013.01); G06F 12/0882 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory subsystem, comprising:
a memory controller, configured to:
directly map a first memory address of a non-aliasing region of an address space to a physical address of a memory, wherein the first memory address and the physical address are matching; and
alias the physical memory location of the memory to a second memory address of an aliasing region of the address space, wherein to alias the physical memory location the memory controller is configured to translate, by address translation logic for the aliasing region, the second memory address of the aliasing region of the address space to the physical address of the memory, wherein the second memory address and the physical address are different;
a cache, configured to:
cache an access to the physical address using the first memory address in a first cache location according to the first memory address; and
cache an access to the physical address using the second memory address in a second cache location according to the second memory address, wherein the first cache location and the second cache location are different.