CPC G06F 12/1009 (2013.01) [G06F 12/0815 (2013.01); G11C 16/0483 (2013.01); G06F 2212/7201 (2013.01); G11C 11/56 (2013.01); G11C 14/0018 (2013.01)] | 20 Claims |
1. A system comprising:
a memory device comprising a quad-level cell (QLC) portion and a single level cell (SLC) portion, the QLC portion comprising multiple QLCs, the SLC portion comprising multiple SLCs, the SLC portion storing a first logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in the QLC portion of the memory device; and
a processing device coupled to the memory device, the processing device comprising a primary flash translation layer (FTL) and a secondary FTL, the primary FTL configured to perform operations comprising:
receiving a request specifying a logical address associated with a host-initiated operation directed at the QLC portion of the memory device;
providing a look-up request to the secondary FTL based on the request, the look-up request specifying the logical address;
the secondary FTL configured to perform operations comprising:
accessing, from a volatile memory component, a second L2P table comprising a mapping between logical addresses and physical addresses in the SLC portion of the memory device;
identifying an entry in the second L2P table corresponding to the logical address;
determining whether the entry in the second L2P table points to a read cache table stored in the volatile memory component;
based on determining the entry does not point to the read cache table, identifying, based on the entry in the second L2P table, a physical location within the SLC portion of the memory device, the physical location within the SLC portion of the memory device corresponding to a portion of the first L2P table that specifies a physical address within the QLC portion of the memory device that corresponds to the logical address;
identifying, based on accessing the portion of the first L2P table, the physical address within the QLC portion of the memory device that corresponds to the logical address;
based on accessing the portion of the first L2P table, adding a new entry to the read cache table that is logically linked to a chunk of read cache in which the portion of the first L2P table is cached; and
providing the physical address to the primary FTL responsive to the look-up request, the primary FTL further configured to execute the host-initiated operation at the physical address within the QLC portion of the memory device that corresponds to the logical address specified by the request.
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