US 11,755,494 B2
Cache line coherence state downgrade
Paul J. Moyer, Fort Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Oct. 29, 2021, as Appl. No. 17/514,776.
Prior Publication US 2023/0138518 A1, May 4, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 13/16 (2006.01); G06F 12/0891 (2016.01); G06F 12/084 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 12/084 (2013.01); G06F 13/1668 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
for a memory access class, detecting at least a threshold number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state;
in response to the detecting, treating first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state;
detecting a reset event for the memory access class; and
in response to detecting the reset event, treating second coherence state agnostic requests for cache lines for the memory access class as coherence state agnostic requests.