CPC G06F 12/0862 (2013.01) [G06F 3/064 (2013.01); G06F 3/0611 (2013.01); G06F 3/0622 (2013.01); G06F 3/0649 (2013.01); G06F 3/0688 (2013.01); G06F 2212/6024 (2013.01); G06F 2212/6026 (2013.01)] | 20 Claims |
1. An apparatus comprising:
processing circuitry; and
memory circuitry comprising a memory array communicatively coupled to the processing circuitry via a bus, wherein the memory circuitry is configured to:
receive a memory access request generated by the processing circuitry via the bus targeting a first data block of the memory array;
access the first data block of the memory array based on a demand time of the memory access request;
determine at least one of a data value correlation parameter determined based at least in part on a raw data value of data bits associated with the first data block and an inter-demand delay correlation parameter determined based at least in part on demand time of the memory access request; and
predictively store data bits associated with a second data block of the memory array at a lower memory level configured to provide faster data read access to the processing circuitry before receiving a subsequent memory access request targeting the second data block based at least in part on the data value correlation parameter, the inter-demand delay correlation parameter, or both.
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