US 11,755,486 B2
Shared buffered memory routing
Debendra Das Sharma, Saratoga, CA (US); Michelle C. Jen, Mountain View, CA (US); and Brian S. Morris, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 21, 2021, as Appl. No. 17/236,692.
Application 17/236,692 is a continuation of application No. 16/140,482, filed on Sep. 24, 2018, granted, now 11,113,196.
Application 16/140,482 is a continuation of application No. 15/665,541, filed on Aug. 1, 2017, abandoned.
Application 15/665,541 is a continuation of application No. 14/670,578, filed on Mar. 27, 2015, granted, now 9,720,838, issued on Aug. 1, 2017.
Prior Publication US 2021/0240623 A1, Aug. 5, 2021
Int. Cl. G06F 12/00 (2006.01); G06F 12/084 (2016.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 12/0806 (2016.01); G06F 12/0808 (2016.01)
CPC G06F 12/084 (2013.01) [G06F 3/061 (2013.01); G06F 3/0635 (2013.01); G06F 3/0673 (2013.01); G06F 12/0806 (2013.01); G06F 12/0808 (2013.01); G06F 13/1673 (2013.01); G06F 13/4282 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/60 (2013.01); G06F 2212/62 (2013.01)] 29 Claims
OG exemplary drawing
 
1. An integrated circuit die comprising:
a plurality of controllers, including a network controller and a shared memory controller;
a processor coupled to the plurality of controllers; and
a multi-lane communication interface coupled to the plurality of controllers, the multi-lane communication interface comprising an electrical sub-block to physically transmit information to an off-die device, the electrical sub-block comprising:
a transmitter to transmit information to the off-die device via a first differential signal path; and
a receiver to receive information from the off-die device via a second differential signal path, the transmitter and the receiver corresponding to one of a plurality of lanes of the multi-lane communication interface;
wherein the multi-lane communication interface supports a first layered protocol stack and a second layer protocol stack, the first layered protocol stack and the second layered protocol stack overlaid on the electrical sub-block, wherein the electrical sub-block is switchable to transmit and receive information in accordance with the first layered protocol stack or to transmit and receive information in accordance with the second layered protocol stack,
wherein the first layered protocol stack comprises a first link layer implemented in a first link layer circuitry, and the second layered protocol stack comprises a second link layer different from the first link layer, the second link layer implemented in second link layer circuitry.