CPC G06F 12/084 (2013.01) [G06F 3/061 (2013.01); G06F 3/0635 (2013.01); G06F 3/0673 (2013.01); G06F 12/0806 (2013.01); G06F 12/0808 (2013.01); G06F 13/1673 (2013.01); G06F 13/4282 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/60 (2013.01); G06F 2212/62 (2013.01)] | 29 Claims |
1. An integrated circuit die comprising:
a plurality of controllers, including a network controller and a shared memory controller;
a processor coupled to the plurality of controllers; and
a multi-lane communication interface coupled to the plurality of controllers, the multi-lane communication interface comprising an electrical sub-block to physically transmit information to an off-die device, the electrical sub-block comprising:
a transmitter to transmit information to the off-die device via a first differential signal path; and
a receiver to receive information from the off-die device via a second differential signal path, the transmitter and the receiver corresponding to one of a plurality of lanes of the multi-lane communication interface;
wherein the multi-lane communication interface supports a first layered protocol stack and a second layer protocol stack, the first layered protocol stack and the second layered protocol stack overlaid on the electrical sub-block, wherein the electrical sub-block is switchable to transmit and receive information in accordance with the first layered protocol stack or to transmit and receive information in accordance with the second layered protocol stack,
wherein the first layered protocol stack comprises a first link layer implemented in a first link layer circuitry, and the second layered protocol stack comprises a second link layer different from the first link layer, the second link layer implemented in second link layer circuitry.
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