US 11,755,484 B2
Instruction block allocation
Jan S. Gray, Bellevue, WA (US); Douglas C. Burger, Bellevue, WA (US); and Aaron L. Smith, Seattle, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jun. 26, 2015, as Appl. No. 14/752,418.
Prior Publication US 2016/0378661 A1, Dec. 29, 2016
Int. Cl. G06F 12/0831 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/30 (2006.01); G06F 12/128 (2016.01)
CPC G06F 12/0833 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/381 (2013.01); G06F 9/382 (2013.01); G06F 9/3804 (2013.01); G06F 9/3806 (2013.01); G06F 9/3826 (2013.01); G06F 9/3828 (2013.01); G06F 9/3836 (2013.01); G06F 9/3838 (2013.01); G06F 9/3842 (2013.01); G06F 9/3846 (2013.01); G06F 9/3851 (2013.01); G06F 9/3853 (2013.01); G06F 9/3869 (2013.01); G06F 9/3891 (2013.01); G06F 11/30 (2013.01); G06F 12/128 (2013.01); G06F 2212/621 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus comprising a processor, the processor comprising:
one or more processing cores configured to fetch and execute a sequence of instruction groups, each of the one or more processing cores comprising functional resources performing operations specified by the sequence of instruction groups; and
one or more core schedulers:
allocating processing cores performing at least a portion of operations specified by child instruction groups of the sequence by a respective aggregated confidence rating, for two or more parent instruction groups, of a child instruction group of the child instruction groups, each of the two or more parent instruction groups being on a respective separate instruction path converging on the child instruction group, and
determining the respective aggregated confidence rating by combining confidence ratings for the converging instruction paths of the two or more parent instruction groups of the child instruction group, and consequently according to the respective aggregated confidence rating, initiating execution of the child instruction group prior to initiating execution of at least one of the child instruction group's two or more parent instruction groups.