CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a memory circuit with a total address space that includes a physical address space and an extended address space, wherein the physical address space includes a pattern address space, and wherein addresses included in the pattern address space correspond to locations where a background data pattern is stored; and
a control circuit configured to:
receive a first read access request including a first read address; and
in response to a determination that the first read address is included in the pattern address space, return the background data pattern while holding the memory circuit in an inactive state.
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