US 11,755,478 B2
Block family combination and voltage bin selection
Michael Sheperek, Longmont, CO (US); Larry J. Koudele, Erie, CO (US); Mustafa N. Kaynak, San Diego, CA (US); and Shane Nowell, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Feb. 8, 2022, as Appl. No. 17/667,326.
Application 17/667,326 is a continuation of application No. 17/008,024, filed on Aug. 31, 2020, granted, now 11,263,134.
Prior Publication US 2022/0156188 A1, May 19, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0802 (2016.01); G06F 12/06 (2006.01); G11C 16/10 (2006.01)
CPC G06F 12/0802 (2013.01) [G06F 12/06 (2013.01); G11C 16/107 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
identifying a plurality of block families associated with a bin boundary of a first voltage bin;
determining, based on values of a data state metric for each of the plurality of block families, at least a first voltage for a first block family of the plurality of block families and a second voltage for a second block family of the plurality of block families; and
responsive to determining that a difference between the first voltage and the second voltage satisfies a block family combination criterion, merging the second block family with the first block family.