CPC G06F 12/0802 (2013.01) [G06F 2212/604 (2013.01)] | 20 Claims |
1. A cache, comprising:
an upstream port;
a downstream port;
a cache memory; and
a control circuit that:
temporarily stores memory access requests received from said upstream port;
checks for dependencies for a new memory access request with older memory access requests temporarily stored therein;
and if one of said older memory access requests creates a false dependency with said new memory access request, drops an allocation of a cache line to said cache memory for said one of said older memory access requests while continuing to process said new memory access request.
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