US 11,755,477 B2
Cache allocation policy
Chintan S. Patel, San Antonio, TX (US); and Girish Balaiah Aswathaiya, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 28, 2021, as Appl. No. 17/563,675.
Claims priority of provisional application 63/251,951, filed on Oct. 4, 2021.
Prior Publication US 2023/0105709 A1, Apr. 6, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/604 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A cache, comprising:
an upstream port;
a downstream port;
a cache memory; and
a control circuit that:
temporarily stores memory access requests received from said upstream port;
checks for dependencies for a new memory access request with older memory access requests temporarily stored therein;
and if one of said older memory access requests creates a false dependency with said new memory access request, drops an allocation of a cache line to said cache memory for said one of said older memory access requests while continuing to process said new memory access request.