CPC G06F 12/0607 (2013.01) [H03M 13/276 (2013.01); H03M 13/2707 (2013.01); H03M 13/6505 (2013.01)] | 20 Claims |
1. A transfer engine for use in a digital signal processing system, the transfer engine comprising:
a first memory port arranged to connect to a memory space, the memory space comprising a first storage region and a second storage region, the first storage region arranged to store a plurality of data items arranged in a first sequence; and
a second memory port arranged to connect to a dynamic random access memory (DRAM);
wherein, during a first transfer, the transfer engine is arranged to read the plurality of data items from the first storage region according to a generated non-linear or non-consecutive sequence of memory read addresses and to write the plurality of data items read from the first storage region to the DRAM, and
wherein, during a subsequent transfer, the transfer engine is arranged to read the plurality of data items from the DRAM according to linear or consecutive address sequences, and to write the plurality of data items to the second storage region according to a generated non-linear or non-consecutive sequence of memory write addresses, such that the plurality of data items are arranged in a second sequence in the second storage region that is different from the first sequence and wherein the second sequence is either interleaved or de-interleaved with respect to the first sequence.
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