US 11,755,474 B2
Tile based interleaving and de-interleaving for digital signal processing
Paul Murrin, Chepstow (GB); Adrian J. Anderson, Chepstow (GB); and Mohammed El-Hajjar, Southampton (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Nov. 18, 2021, as Appl. No. 17/529,954.
Application 17/529,954 is a continuation of application No. 16/845,303, filed on Apr. 10, 2020, granted, now 11,210,217.
Application 16/845,303 is a continuation of application No. 16/381,268, filed on Apr. 11, 2019, granted, now 10,657,050, issued on May 19, 2020.
Application 16/381,268 is a continuation of application No. 13/794,796, filed on Mar. 12, 2013, granted, now 10,296,456, issued on May 21, 2019.
Claims priority of application No. 1215425 (GB), filed on Aug. 30, 2012.
Prior Publication US 2022/0075723 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/06 (2006.01); H03M 13/27 (2006.01); H03M 13/00 (2006.01)
CPC G06F 12/0607 (2013.01) [H03M 13/276 (2013.01); H03M 13/2707 (2013.01); H03M 13/6505 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transfer engine for use in a digital signal processing system, the transfer engine comprising:
a first memory port arranged to connect to a memory space, the memory space comprising a first storage region and a second storage region, the first storage region arranged to store a plurality of data items arranged in a first sequence; and
a second memory port arranged to connect to a dynamic random access memory (DRAM);
wherein, during a first transfer, the transfer engine is arranged to read the plurality of data items from the first storage region according to a generated non-linear or non-consecutive sequence of memory read addresses and to write the plurality of data items read from the first storage region to the DRAM, and
wherein, during a subsequent transfer, the transfer engine is arranged to read the plurality of data items from the DRAM according to linear or consecutive address sequences, and to write the plurality of data items to the second storage region according to a generated non-linear or non-consecutive sequence of memory write addresses, such that the plurality of data items are arranged in a second sequence in the second storage region that is different from the first sequence and wherein the second sequence is either interleaved or de-interleaved with respect to the first sequence.