CPC G06F 11/273 (2013.01) [G06F 1/04 (2013.01); G06F 11/2236 (2013.01); G06F 15/7807 (2013.01); H03K 19/20 (2013.01)] | 22 Claims |
18. A debugging unit, comprising:
a register, adapted to sample input data under control of a clock signal, wherein the register includes;
an input interface, adapted to receive the input data;
the enable interface, adapted to receive the control signal;
a clock interface, adapted to receive the clock signal; and
an output interface, adapted to output data;
wherein the register is adapted to;
in a validity period of the clock signal, if a clock enable signal and the enable signal of the register are both on high levels, sample the input data; or
in the validity period of the clock signal, if the clock enable signal and the enable signal of the register are not both on high levels, skip sampling the input data; and
a clock control unit, adapted to generate the control signal based on the clock enable signal to control the clock signal, so that the register is controlled to sample the input data in the validity period of the clock signal when the control signal is valid, wherein the clock control unit is coupled to an enable interface of the register, and further adapted to generate a control signal based on the clock enable signal and an enable signal of the register, and wherein the clock control unit includes a data selector, adapted to select, under control of the enable signal of the register, whether to output the clock enable signal to the enable interface of the register.
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