US 11,755,412 B2
Semiconductor device with modified command and associated methods and systems
Todd M. Buerkle, Boise, ID (US); Debra M. Bell, Boise, ID (US); and Joshua E. Alzheimer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 1, 2021, as Appl. No. 17/539,714.
Application 17/539,714 is a continuation of application No. 16/554,931, filed on Aug. 29, 2019, granted, now 11,200,118.
Prior Publication US 2022/0091938 A1, Mar. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 29/38 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 11/1012 (2013.01); G06F 11/1052 (2013.01); G11C 29/38 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array corresponding to a plurality of memory addresses each corresponding both to a first portion of the memory array configured to store user data and to a second portion of the memory array configured to 1) store error-correcting code (ECC) data corresponding to the user data when an ECC function of the apparatus is enabled and 2) store non-ECC data not corresponding to the user data when the ECC function is disabled; and
circuitry configured to:
receive a command directed to the memory array;
access the second portion of the memory array in response to the command; and
communicate either the ECC data or the non-ECC data to or from the second portion of the memory array in response to the command.