US 11,755,411 B2
Error rate reduction in a non-volatile memory (NVM), including magneto-resistive random access memories (MRAMS)
Anirban Roy, Austin, TX (US); and Nihaar N. Mahatme, Austin, TX (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Jun. 29, 2022, as Appl. No. 17/809,655.
Application 17/809,655 is a division of application No. 17/247,376, filed on Dec. 9, 2020, granted, now 11,379,307.
Prior Publication US 2022/0327020 A1, Oct. 13, 2022
Int. Cl. G06F 11/10 (2006.01); G11C 11/16 (2006.01)
CPC G06F 11/1072 (2013.01) [G11C 11/1675 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of programming a nonvolatile magnetoresistive random access memory (MRAM) device, the method comprising:
before a solder reflow process, combining separate words of MRAM data to form longer words of MRAM data;
assigning to each longer word a number of error correction code (ECC) bits in accordance with a first bit error correction rate that is less than a total number of error correction code (ECC) bits in accordance with a second bit error correction rate originally allocated to the respective separate words combined to form the longer word;
programming data into data bit cells of the MRAM as the longer words, wherein the programming includes, for each of the longer words:
inverting ones and zeros of each respective separate word when storing the respective separate word into the data bits cells as the longer word when the number of zeros is greater than the number of ones to be programmed in the data bit cells;
storing an inversion indicator bit for each respective separate word into the data bit cells to indicate whether the respective separate word has been inverted due to a number of zeros being greater than a number of ones to be programmed in the data bit cells; and
storing ECC bits generated from the longer word in accordance with the first bit error correction rate into the data bit cells.