US 11,755,406 B2
Error identification in executed code
Antonino Mondello, Messina (IT); and Alberto Troia, Munich (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 2, 2022, as Appl. No. 17/734,837.
Application 17/734,837 is a continuation of application No. 17/119,676, filed on Dec. 11, 2020, granted, now 11,321,168.
Application 17/119,676 is a continuation of application No. 16/362,751, filed on Mar. 25, 2019, granted, now 10,872,010, issued on Dec. 22, 2020.
Prior Publication US 2022/0261309 A1, Aug. 18, 2022
Int. Cl. G06F 11/10 (2006.01); B60W 50/02 (2012.01); B60W 50/14 (2020.01)
CPC G06F 11/1008 (2013.01) [B60W 50/0205 (2013.01); B60W 50/14 (2013.01); G06F 11/1076 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first memory device;
a second memory device; and
circuitry configured to:
receive read data from the first memory device;
receive an error correcting code (ECC);
compare the read data of the first memory device to the ECC provided by the second memory device by comparing a hash function corresponding to the data and a digest corresponding to the ECC; and
take an action in response to the comparison indicating that the ECC identified an error in the read data of the first memory device.