US 11,755,399 B1
Bit error rate reduction technology
Shuo-Nan Hung, Hsinchu (TW); and Chun-Hsiung Hung, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on May 24, 2022, as Appl. No. 17/752,502.
Int. Cl. G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/076 (2013.01) [G06F 3/065 (2013.01); G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 11/1044 (2013.01); G06F 3/0685 (2013.01)] 19 Claims
OG exemplary drawing
 
9. A method of redundantly storing data in a memory array of an integrated circuit (IC), the memory array including one or more arrays of memory cells, the IC including an address register and computation-in-memory (CIM) logic coupled with the memory array, the method comprising:
holding, in the address register, at least one address of a securely stored file;
outputting, by the address register, three or more addresses of the securely stored file; and
implementing the CIM logic to perform a majority function on three or more bits of the securely stored file to redundantly store the three or more bits in the memory array in three or more different locations, associated with the three or more addresses, in the memory array.