a processor core executing event-based programming code to interface a plurality of isolated execution contexts with a set of external communication channel hardware devices using time division multiplexing;

an event latch connected and configured to store n hardware events as single-bit signals received from the set of external communication channel hardware devices, where each hardware event is remembered until an acknowledgment is received from the processor core signals that the hardware event has been processed;

a timer circuit that generates a sequence of timer interrupt signals; and

a masking circuit connected and configured to mask the n hardware events stored in the event latch with an n-bit event mask in response to each timer interrupt signal, where each n-bit event mask is associated with a different isolated execution context running on the processor core such that each isolated execution context is allowed to process only a masked subset of the hardware events specified by the n-bit event mask to ensure freedom from interference between the plurality of isolated execution contexts when communicating with the set of external communication channel hardware devices.