CPC G06F 9/3881 (2013.01) [G06F 9/382 (2013.01); G06F 9/383 (2013.01); G06F 9/3877 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a processor configured to execute processor instructions;
a coprocessor configured to execute coprocessor instructions, wherein the processor instructions and the coprocessor instructions appear together in code sequences fetched by the processor, wherein the processor is configured to provide the coprocessor instructions to the coprocessor; and
a coprocessor prefetcher configured to:
monitor a code sequence fetched by the processor;
in response to identifying a presence of the coprocessor instructions in the code sequence, capture memory addresses, generated by the processor, of operand data for the coprocessor instructions; and
issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.
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