CPC G06F 9/3814 (2013.01) [G06F 9/30018 (2013.01); G06F 9/30043 (2013.01); G06F 9/3816 (2013.01); G06F 9/3877 (2013.01); G06F 9/4881 (2013.01); G06F 9/522 (2013.01)] | 20 Claims |
1. A processor comprising:
a coprocessor issue circuit comprising a queue circuit, wherein the processor is configured to store coprocessor instructions for a coprocessor to which the processor is coupled in the queue circuit; and
an interface unit coupled to the coprocessor issue circuit, the interface unit comprising a buffer including a plurality of entries; wherein:
the coprocessor issue circuit is configured to issue one or more first coprocessor instructions from the queue circuit to the interface unit and to subsequently issue one or more second coprocessor instructions from the queue circuit to the interface unit;
the interface unit is configured to allocate a first entry of the plurality of entries based on issuance of the one or more first coprocessor instructions, and to write first data corresponding to the one or more first coprocessor instructions to the first entry;
the interface unit is configured to merge second data corresponding to the one or more second coprocessor instructions in the first entry based on issuance of the one or more second coprocessor instructions;
the interface unit is configured to close the first entry and to write a command to the first entry;
the command comprises a plurality of opcodes corresponding to respective ones of the one or more first coprocessor instructions and the one or more second coprocessor instructions;
the first data comprises source data from processor registers specified by the one or more first coprocessor instructions and the second data comprises source data from processor registers specified by the one or more second coprocessor instructions; and
the source data further specifies the first coprocessor instructions and the second coprocessor instructions identified by the plurality of opcodes.
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