US 11,755,327 B2
Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices
Melinda Joyce Brown, Raleigh, NC (US); and Michael Scott Mcilvaine, Raleigh, NC (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Mar. 2, 2020, as Appl. No. 16/806,342.
Prior Publication US 2021/0271480 A1, Sep. 2, 2021
Int. Cl. G06F 9/32 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/54 (2006.01)
CPC G06F 9/321 (2013.01) [G06F 9/30054 (2013.01); G06F 9/381 (2013.01); G06F 9/3867 (2013.01); G06F 9/544 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A processor-based device, comprising:
a processing element (PE) comprising:
an execution pipeline circuit comprising an instruction processing portion and a data access portion;
a literal pool buffer;
a literal data access logic circuit; and
a branch target buffer comprising a plurality of branch target buffer entries;
the PE configured to:
detect, by the literal data access logic circuit, a literal pool within an instruction stream by being configured to:
detect an unconditional PC-relative branch instruction in the instruction stream; and
responsive to detecting the unconditional PC-relative branch instruction in the instruction stream, store data related to a size and an address of the literal pool in a branch target buffer entry of the plurality of branch target buffer entries corresponding to the unconditional PC-relative branch instruction;
fetch the literal pool based on the data related to the size and the address of the literal pool stored in the branch target buffer entry of the plurality of branch target buffer entries corresponding to the unconditional PC-relative branch instruction;
store the literal pool within the literal pool buffer by being configured to store data between the unconditional PC-relative branch instruction and a target instruction as the literal pool within the literal pool buffer;
detect, by the literal data access logic circuit, a program counter (PC)-relative load instruction within a fetch window comprising a plurality of instructions of the instruction stream;
determine that literal data corresponding to the PC-relative load instruction is stored in the literal pool buffer; and
responsive to determining that the literal data corresponding to the PC-relative load instruction is stored in the literal pool buffer:
retrieve, within the instruction processing portion of the execution pipeline circuit by the literal data access logic circuit, the literal data from the literal pool buffer; and
execute the PC-relative load instruction using the literal data as an immediate value to be loaded.