US 11,755,325 B2
Instruction handling for accumulation of register results in a microprocessor
Brian W. Thompto, Austin, TX (US); Maarten J. Boersma, Holzgerlingen (DE); Andreas Wagner, Weil im Schönbuch (DE); Jose E. Moreira, Irvington, NY (US); Hung Q. Le, Austin, TX (US); Silvia Melitta Mueller, St. Ingbert (DE); and Dung Q. Nguyen, Austin, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 27, 2021, as Appl. No. 17/458,717.
Application 17/458,717 is a continuation of application No. 16/555,640, filed on Aug. 29, 2019, granted, now 11,132,198.
Prior Publication US 2022/0050682 A1, Feb. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30098 (2013.01) [G06F 9/3012 (2013.01); G06F 9/3001 (2013.01); G06F 9/3013 (2013.01); G06F 9/30036 (2013.01); G06F 9/30109 (2013.01); G06F 9/384 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of processing instructions in a processor, the method comprising:
providing a main register file associated with the processor, the main register file having a plurality of main register file entries for storing data;
providing an accumulator register file associated with a dense math execution unit, the accumulator register file having a plurality of accumulator register file entries for storing data;
mapping at least one of the plurality of main register file entries to at least one of the plurality of accumulator register file entries;
performing dense math operations with the dense math execution unit;
writing results of the dense math operations performed with the dense math execution unit to the accumulator register file; and
writing data in the at least one of the plurality of accumulator register file entries to the at least one of the main register file entries to which the at least one of the plurality of accumulator register entries is mapped.