US 11,755,246 B2
Efficient rank switching in multi-rank memory controller
Guanhao Shen, Austin, TX (US); and Ravindra Nath Bhargava, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 24, 2021, as Appl. No. 17/357,007.
Prior Publication US 2022/0413759 A1, Dec. 29, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for a memory controller to select memory access requests to provide to a memory channel having a plurality of ranks, comprising:
initiating a burst of write accesses;
performing a write access to a current rank;
determining whether the memory controller is near an end of the burst of write accesses;
in response to the memory controller not being near the end of the burst of write accesses:
selectively switching said current rank; and
repeating said performing and said determining;
in response to the memory controller being near the end of the burst of write accesses:
continuing said burst of write accesses to said current rank a predetermined number of times;
waiting a write-to-read turnaround time; and
starting a read burst when any read access becomes timing eligible.