US 11,755,214 B2
Sequential data optimized sub-regions in storage devices
David Aaron Palmer, Boise, ID (US); Sean L. Manion, Boise, ID (US); Jonathan Scott Parry, Boise, ID (US); Stephen Hanna, Fort Collins, CO (US); Qing Liang, Boise, ID (US); Nadav Grosz, Broomfield, CO (US); Christian M. Gyllenskog, Meridian, ID (US); and Kulachet Tanpairoj, Santa Clara, CA (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 23, 2022, as Appl. No. 17/702,217.
Application 17/702,217 is a continuation of application No. 17/129,087, filed on Dec. 21, 2020, granted, now 11,294,585.
Application 17/129,087 is a continuation of application No. 16/237,134, filed on Dec. 31, 2018, granted, now 10,871,907.
Prior Publication US 2022/0214821 A1, Jul. 7, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0631 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A storage system comprising:
a memory array;
a random access memory configured to store at least a portion of one or more logical-to-physical (L2P) mapping tables; and
a memory controller including processing circuitry including one or more processors, wherein the memory controller is configured to perform operations including:
partitioning the memory array into multiple portions having non-overlapping logical block addressing (LBA) ranges;
assigning performance levels to multiple mapping table entries respectively corresponding to the multiple portions of the memory array based on usage designations for the multiple portions, where a first at least one of the performance levels is not equal to a second at least one of the performance levels;
storing at least a portion of the multiple mapping table entries in the random access memory.