CPC G06F 3/0631 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7204 (2013.01)] | 20 Claims |
1. A storage system comprising:
a memory array;
a random access memory configured to store at least a portion of one or more logical-to-physical (L2P) mapping tables; and
a memory controller including processing circuitry including one or more processors, wherein the memory controller is configured to perform operations including:
partitioning the memory array into multiple portions having non-overlapping logical block addressing (LBA) ranges;
assigning performance levels to multiple mapping table entries respectively corresponding to the multiple portions of the memory array based on usage designations for the multiple portions, where a first at least one of the performance levels is not equal to a second at least one of the performance levels;
storing at least a portion of the multiple mapping table entries in the random access memory.
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