US 11,755,210 B2
Unauthorized memory access mitigation
Richard C. Murphy, Boise, ID (US); Shivam Swami, Folsom, CA (US); Naveh Malihi, University City, MO (US); Anton Korzh, Boise, ID (US); and Glen E. Hush, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 4, 2022, as Appl. No. 17/665,307.
Application 17/665,307 is a continuation of application No. 16/235,303, filed on Dec. 28, 2018, granted, now 11,256,427.
Prior Publication US 2022/0155978 A1, May 19, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0622 (2013.01) [G06F 3/0638 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array;
a key register configured to store a first key used to determine whether access commands are allowed access to a protected region of the memory array;
a protected region register configured to store addresses defining the protected region;
an access count register to store an access count;
a mode register; and
control circuitry configured to:
responsive to receiving a security mode initialization command from a host:
store the first key in the key register;
store a first address corresponding to the memory array in the protected region register, wherein the first address is a protected address and the first key corresponds to the protected address;
responsive to storing the first key and storing the first address, set the mode register to a locked mode;
responsive to determining that the mode register is in the locked mode, determine whether the access count is less than a threshold;
responsive to determining that the access count is less than the threshold, determine whether to allow access to a second address corresponding to an access command based on whether the second address is within the protected region and based on whether a second key from a number of keys corresponding to the access command from a number of access commands matches the first key stored in the key register, wherein each key of the number of keys is provided with a different access command of the number of access commands; and
responsive to allowing access to the second address, increment the access count register and enable a row driver;
reset the access count register responsive to a lapse of time without receiving additional access commands to the protected region.