US 11,755,206 B2
Bank to bank data transfer
Thanh K. Mai, Allen, TX (US); Gary L. Howe, Plano, TX (US); and Daniel B. Penney, Wylie, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 18, 2021, as Appl. No. 17/178,889.
Application 17/178,889 is a continuation of application No. 16/541,764, filed on Aug. 15, 2019, granted, now 10,929,023.
Application 16/541,764 is a continuation of application No. 15/189,900, filed on Jun. 22, 2016, granted, now 10,387,046, issued on Aug. 20, 2019.
Prior Publication US 2021/0173557 A1, Jun. 10, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 8/00 (2006.01); G06F 13/16 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0646 (2013.01); G06F 3/0647 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 13/161 (2013.01); G11C 8/00 (2013.01); Y02D 10/00 (2018.01)] 18 Claims
OG exemplary drawing
 
1. A system, comprising:
a host configured to generate commands; and
a memory device, coupled to the host, comprising:
a plurality of banks of memory cells;
a controller coupled to the plurality of banks configured to:
receive a command from the host with instructions to transfer data between the plurality of banks, the command including source bank information and destination bank information; and
transfer the data on an internal data bus between the plurality of banks of memory cells via internal data path operations that use the source bank information to identify a source bank to read the data from and the destination bank information to identify a destination bank to write the data to, wherein the internal data path operations include performing a silent read command that transfers data from the plurality of banks to a number of bidirectional buffers isolated from a number of DQs.