CPC G06F 1/3237 (2013.01) [G06F 1/3209 (2013.01); G06F 1/3296 (2013.01); H04W 52/0229 (2013.01); H04W 52/0235 (2013.01)] | 20 Claims |
1. A processor comprising:
a central processing unit (CPU);
a performance controller having a performance register, the performance register having a plurality of values associated with incrementally increasing performance and incrementally increasing power consumption;
a high speed bus coupled to a low power static random access memory (LPSRAM), a high speed static random access memory (HSSRAM), and to the CPU;
a low speed bus coupled to the CPU and the performance register;
a bridge coupling the high speed bus to the low speed bus;
the performance controller, for each discrete value of performance register, associating a CPU voltage from a CPU voltage source, a CPU clock speed from a CPU clock source, and enabling or disabling the LPSRAM and HSSRAM;
the low speed bus coupled to an RF energy detector periodically storing samples of RF energy level into the LPSRAM, wherein an increase in the RF energy level of the samples causes the performance controller to change a value in the performance register to a higher performance level.
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