US 11,755,093 B2
Power disable of memory sub-system
Manohar Karthikeyan, Longmont, CO (US); and Mehdi Partou, Erie, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 16, 2022, as Appl. No. 17/696,543.
Application 17/696,543 is a continuation of application No. 16/714,503, filed on Dec. 13, 2019, granted, now 11,307,632.
Claims priority of provisional application 62/924,866, filed on Oct. 23, 2019.
Prior Publication US 2022/0206557 A1, Jun. 30, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G11C 7/10 (2006.01); G06F 1/14 (2006.01); G06F 1/3225 (2019.01); G06F 1/3234 (2019.01); G06F 1/3246 (2019.01)
CPC G06F 1/3225 (2013.01) [G06F 1/14 (2013.01); G06F 1/3246 (2013.01); G06F 1/3253 (2013.01); G06F 1/3275 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a power disable circuit coupled to a bus connector of a host system and to power circuitry adapted to power on and off the memory device, the power disable circuit comprising:
a first field effect transistor (FET) and a second FET with sources mutually coupled and gates to receive a power disable (PWDIS) signal of the bus connector, wherein, in response to an asserted input of the PWDIS signal at a second gate of the second FET, a drain of the first FET is left floating;
a latch circuit to assert an output in response to a general purpose input/output signal received from a processing device; and
a third FET coupled to the drain of the first FET and to the output of the latch circuit, wherein in response to assertion of the output of the latch circuit, the third FET is to signal to the power circuitry to cut power to the memory device.