CPC H10N 70/068 (2023.02) [H10B 61/00 (2023.02); H10B 63/80 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02); H10N 70/023 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/841 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a memory stack on a first dielectric layer;
a sidewall spacer on the memory stack;
a conductive cap on the sidewall spacer and the memory stack; and
an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.
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