US 11,751,460 B2
Display panel, method of manufacturing the same and display device
Yipeng Chen, Beijing (CN); Lujiang Huangfu, Beijing (CN); and Libin Liu, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/762,962
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Apr. 15, 2021, PCT No. PCT/CN2021/087367
§ 371(c)(1), (2) Date Mar. 23, 2022,
PCT Pub. No. WO2021/227759, PCT Pub. Date Nov. 18, 2021.
Claims priority of application No. 202010388571.2 (CN), filed on May 9, 2020.
Prior Publication US 2022/0336542 A1, Oct. 20, 2022
Int. Cl. H10K 59/131 (2023.01); H10K 59/35 (2023.01); G09G 3/3233 (2016.01); H10K 59/126 (2023.01); H10K 59/12 (2023.01)
CPC H10K 59/353 (2023.02) [G09G 3/3233 (2013.01); H10K 59/126 (2023.02); H10K 59/131 (2023.02); H10K 59/352 (2023.02); G09G 2300/0452 (2013.01); G09G 2300/0842 (2013.01); H10K 59/1201 (2023.02)] 15 Claims
OG exemplary drawing
 
15. A method of manufacturing a display panel, wherein the display panel includes a plurality of sub-pixel areas arranged in an array, sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each of the plurality of sub-pixel area group includes at least two adjacent sub-pixel areas; the method includes:
forming an initialization signal line layer, a connection layer, an anode layer and a first auxiliary signal line layer on a substrate;
the initialization signal line layer includes an initialization signal line pattern arranged in each of the plurality of sub-pixel areas;
the connection layer includes a connection pattern arranged in each of the plurality of sub-pixel areas, at least part of the connection pattern extends along the first direction, and the connection pattern is coupled to the initialization signal line pattern in a sub-pixel area where the connection pattern is located; connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion;
the anode layer includes a plurality of anode patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, the plurality of anode patterns are arranged at intervals, and an anode spacing area is formed between adjacent anode patterns;
the first auxiliary signal line layer is a grid structure, and at least part of the first auxiliary signal line layer is located in the anode spacing area, and is insulated from the anode pattern, the connection pattern in each of the plurality of sub-pixel area groups is coupled to the first auxiliary signal line layer.