US 11,751,449 B2
Array substrate, display panel, and display device
Zhongjie Wang, Beijing (CN); and Zhongliu Yang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/271,035
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed May 29, 2020, PCT No. PCT/CN2020/093302
§ 371(c)(1), (2) Date Feb. 24, 2021,
PCT Pub. No. WO2020/248837, PCT Pub. Date Dec. 17, 2020.
Claims priority of application No. 201910504667.8 (CN), filed on Jun. 12, 2019.
Prior Publication US 2021/0327997 A1, Oct. 21, 2021
Int. Cl. H10K 59/131 (2023.01); H10K 59/123 (2023.01)
CPC H10K 59/131 (2023.02) [H10K 59/123 (2023.02)] 17 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a base substrate;
a plurality of pixel units arranged in an array on the base substrate; and
a first power line and a second power line arranged on the base substrate and configured to respectively provide a first power signal and a second power signal to the plurality of pixel units,
wherein at least one of the pixel units comprises:
a first-color light emitting device;
a second-color light emitting device;
a first pixel driving circuit configured to drive the first-color light emitting device, wherein the first-color light emitting device is a blue light emitting device; and
a second pixel driving circuit configured to drive the second-color light emitting device;
wherein the first pixel driving circuit is electrically connected to the first power line, the second pixel driving circuit is electrically connected to the second power line, and the first power line and the second power line are insulated from each other,
wherein the first power line comprises:
a first sub-line extending in a first direction and electrically connected to the first pixel driving circuit;
a second sub-line extending in a second direction intersecting the first direction, wherein the second sub-line is electrically connected to the first sub-line; and
a third sub-line arranged around the plurality of pixel units, wherein the third sub-line is electrically connected to the first sub-line and the second sub-line, and the third sub-line is a closed loop line.